Digital electronic logic devices, such as microprocessors, field-programmable gate arrays (“FPGAs”), complex logic devices (“CPLDs”), and application-specific integrated circuits (“ASICs”) use a digital clock signal to synchronize operations of different portions of the logic device. However, the digital clock signal accumulates various amounts of delay as it travels along different paths. Variation in when a clock pulse occurs because of delay is called clock skew. Clock skew (also called “phase skew”) is intentional in some cases, such as in the outputs of a digital clock manager (“DCM”). For example, a DCM might provide clock outputs with zero phase skew, ninety degrees of phase skew, one-hundred and eighty degrees of phase skew, and two-hundred and seventy degrees of phase skew. It is very desirable to characterize clock skew in a digital electronic device for various paths of the clock signal; however, clock skew can be obscured by clock jitter.
Jitter causes successive clock pulses to occur slightly before or slightly after the expected clock pulse. Thus, it is important to remove the contribution of jitter when measuring clock skew. One way to characterize jitter of a clock signal is to measure the edge placements of several successive clock pulses using a test instrument, such as a high-speed oscilloscope, and then average the edge placement (time) to determine the average clock timing. Such measurements are often done on a test bench and take a relatively long time. This often results in such measurements of clock skew being made on relatively few units. It is desirable to be able to perform clock timing averaging on more units, and particularly desirable to be able to perform clock timing averaging and associated clock skew measurements in an ATE environment.